Memory devices have become ubiquitous over the last several years, and are now the backbone of almost every new piece of technology, such as mobile phones, MP3 players, palmtop computing devices, internet appliances, and digital cameras, to name just a few. Also, they remain a key component in personal computers, networks, and servers. Though the use of memory devices has increased, competition in the memory marketplace has become fierce, and the price that memories command continues to decrease. Manufactures seek to reduce every element that makes up the cost of their products. One of these is the cost of testing.
Manufactures of integrated circuit memory devices test each chip before assembling it in a package. This reduces the costs associated with building integrated circuits that are later discarded. The packaged parts are retested to eliminate any devices which are inadvertently destroyed during assembly.
The costs associated with these tests can be high, and are often higher than the cost of the actual silicon chip. Test machines are expensive, and an operator must be nearby to facilitate the process. If it takes longer to test a device, then more testers and operators are needed. This results in a higher testing cost per unit. Some manufactures have even found it more cost effective to skip the first round of testing, even though this leads to building bad parts which are later thrown away.
Also, the complexity of these devices has become such that to improve their testability, additional circuitry not used in the device""s operating mode is included on-chip. But this circuitry adds to the chip die size, making it more expensive. This can be considered as a part of the total test cost.
Optimal testing of these devices includes the use of various patterns, such as a solid, row stripe, column stripe, and checkerboard. These are explained further below. Unfortunately, the use of these patterns can increase test time. What is needed are methods and apparatus for testing memory devices using these patterns, with minimal additional circuitry requirements, in a fast efficient manner.
Accordingly, embodiments of the present invention provide for effectively shortening device test time by testing multiple devices simultaneously. This is done by reducing the number of pins accessed by a test system. Specifically, one device pin provides the input data for several memory cells. In this way, a tester""s limited number of probes are allocated among multiple devices, and the tester can test more than one device at a time.
These embodiments of the present invention further provide methods and apparatus for testing memory devices in solid, row stripe, column stripe, checkerboard, and other patterns; they compensate for the reduction in input signals and allow full testing using these patterns. These methods and apparatus require little additional circuitry despite having fewer input signals available.
One exemplary embodiment of the present invention provides a method including receiving a first input data bit having a first polarity, and receiving a second input data bit having a second polarity, wherein the second polarity is the complement of the first polarity. The method also includes writing the first input data bit to a first portion of a plurality of memory cells, writing the second input data bit to a second portion of a plurality of memory cells, and reading data bits from the first and second portions of the plurality of memory cells. An active signal is generated if the data bits read from the first portion of the plurality of memory cells and complements of the data bits read from the second portion of the plurality of memory cells all have the same polarity.
A further embodiment of the present invention provides a memory device. This device includes an input/output pad, a first plurality of write buffers coupled to the input/output pad, and a first plurality of multiplexers coupled to the input/output pad a second plurality of write buffers, each coupled to one of the first plurality of multiplexers. Also included are a first plurality of memory cells, each selectively coupled to one of the first plurality of write buffers, and a second plurality of memory cells, each selectively coupled to one of the second plurality of write buffers. A first plurality of sense amplifiers, each selectively coupled to one of the first plurality of memory cells, a second plurality of sense amplifiers, each selectively coupled to one of the second plurality of memory cells, and a second plurality of multiplexers, each coupled to one of the second plurality of sense amplifiers are also included.
Yet a further exemplary embodiment of the present invention provides a memory device including means for writing data having a first polarity to a first plurality of memory cells, means for writing data having either the first polarity, or a complement of the first polarity to a second plurality of memory cells, and means for reading data from the first plurality of memory cells. Also included are means for reading data from the second plurality of memory cells, and means for checking the polarity of the data from each of the first plurality of memory cells and the second plurality of memory cells.
Another exemplary embodiment of the present invention provides a method of testing a memory device, the memory device including a plurality of memory cells arranged in rows and columns, each of which are written to by one of either a plurality of even write circuits, or a plurality of odd write circuits, wherein the memory cells that are written to by an even write circuit are read by an even read circuit, and the memory cells that are written to by an odd write circuit are read by an odd read circuit. The method itself includes selecting a first row of memory cells, selecting a first column of memory cells, and providing an input bit. A status bit is checked to determine if it is active, and if it is then the input bit is provided to both the odd and even write circuits; else the input bit is provided to the odd write circuits, and a complement of the input bit is provided to the even write circuits. Data is then written from the even and odd write circuits to memory cells in the selected row and column.